MOS transistor devices are well known and are used in a wide variety of electronic systems and applications. In advanced complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) process technology, there has been a push toward using lower voltage transistors. In a 40 nanometer (nm) IC fabrication process, for example, 1.8-volt transistors are being readily adopted. However, despite the push to utilize lower voltage transistors, there is still a need for high voltage tolerance in certain applications (e.g., failsafe input/output (IO) circuits) that may require interfacing with higher voltages (e.g., 5 volts).
One problem effecting MOS transistors used in a high voltage application is that the gate oxide of a MOS transistor device typically cannot tolerate the application of a high voltage signal to the gate of the device. Two reliability mechanisms known to contribute to gate oxide failure in a MOS device include negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB).
Conventional high voltage tolerant IO interface circuits typically employ stacked metal-oxide-semiconductor (MOS) devices. An example of this configuration is described in U.S. Pat. No. 6,388,475 to Clark et al. While this circuit configuration may help alleviate overvoltage stress on individual devices by distributing the voltage across two or more devices, some high voltage tolerant failsafe specifications require that the circuit tolerate a prescribed voltage even when power to the circuit is removed. This creates a problem for the stacked MOS device approach. Additionally, using stacked MOS devices often requires complex bias generation circuitry and utilizes more area in the IC compared to a non-stacked device arrangement and is therefore undesirable.
Another known approach to forming a high voltage tolerant MOS device is to increase a thickness of the oxide in the MOS device to accommodate the higher voltage. One disadvantage of this approach, however, is that it requires additional IC fabrication steps, which increase overall cost.
Accordingly, there exists a need for a high voltage tolerant MOS transistor which does not suffer from one or more of the above-noted problems associated with conventional MOS transistors.